Test compression technology was invented to address the problem of escalating test-pattern size. Compression allows more test vectors to be applied to an IC in a shorter time and with fewer tester ...

As chips become more heterogeneous with more integrated functionality, testing them presents increasing challenges — particularly for high-speed system-on-chip (SoC) designs with limited test pin ...

In New test points slash ATPG test pattern count, I described a new type of test point technology used with scan compression for device testing. The key benefit of using test points with embedded ...

Semiconductor chips have been evolving to meet the demands of rapidly transforming applications, and so has the test technology to meet the test goals of those chips. Going back two decades or so, the ...